`include "mips.h"

module bp (I2, Memaddr, WBaddr, Memresult, WBresult, RSreg, RTreg, RSbypassed, RTbypassed);

input	[31:0]	I2;	// Stage 3 instruction
input [4:0] Memaddr;	// Stage 4 dest address
input [4:0] WBaddr;		// Stage 5 dest address
input [31:0] Memresult;	// Stage 4 result
input [31:0] WBresult;	// Stage 5 result
input [31:0] RSreg;	// Stage 4 result
input [31:0] RTreg;	// Stage 5 result

output	[31:0]	RSbypassed;	// Stage 3 source operand
reg		[31:0]	RSbypassed;
output	[31:0]	RTbypassed;	// Stage 3 source operand
reg		[31:0]	RTbypassed;

//	Bypassing support for data dependencies
always @(Memaddr or WBaddr or Memresult or WBresult or I2 or RSreg or RTreg)	begin
	if((I2[`rs] == Memaddr) && (Memaddr != `r0)) begin
		RSbypassed = Memresult;
	end
	else if((I2[`rs] == WBaddr) && (WBaddr != `r0)) begin
		RSbypassed = WBresult;
	end
	else begin
		RSbypassed = RSreg;
	end

	if((I2[`rt] == Memaddr) && (Memaddr != `r0)) begin
		RTbypassed = Memresult;
	end
	else if((I2[`rt] == WBaddr) && (WBaddr != `r0)) begin
		RTbypassed = WBresult;
	end
	else begin
		RTbypassed = RTreg;
	end
end

endmodule
